1. Field of the Invention
The present invention generally relates to a bit line sense amplifier, and more specifically, to a bit line sense amplifier for inhibiting increase of an offset voltage by offsetting an effect due to characteristic inconsistency of devices which results from difference in space location of devices.
2. Description of the Prior Art
In a DRAM, a sense amplifier as a device for sensing insignificant information stored in a cell and then amplifying the sensed information is positioned in two paired bit lines BL and /BL. However, since the width between the paired bit lines BL and /BL is so narrow that symmetrical NMOS transistors or PMOS transistors are not arranged in parallel but in serial. As a result, the symmetrical NMOS transistors or PMOS transistors which are required to have the same electrical characteristics have relative difference in location to adjacent circuits.
FIG. 1 is a circuit layout diagram illustrating the connection relation ship in a conventional bit line sense amplifier.
Referring to FIG. 1, a NMOS transistor N1 is positioned at the edge of a P-well while a NMOS transistors N2 symmetrically located to the NMOS transistor N1 is positioned at the middle of the p-well. In this way, a relative difference in location of devices which are symmetrically positioned to the adjacent circuits causes an electrical characteristic difference in the two devices, which affects an offset voltage of the bit line sense amplifier comprised of two devices.
FIG. 2 is a diagram illustrating one cause to differentiate a threshold voltage VT depending on location of a device in a well.
In a common ion-implantation process, ions are implanted in a substrate aslant with some angle in a vertical direction of the substrate, and then the substrate is rotated for homogeneous distribution of impurities. Due to the rotation, a part of the ions implanted in the edge of the well are reflected and diffused at a side wall of a photoresist film, and dropped on the substrate. As a result, distribution of concentration of the impurities in the edge of the well is differentiated from that in the middle of the well.
FIG. 3 is a diagram illustrating a simulation result that shows a difference of a local threshold voltage VT of a device depending on location in a well.
As shown in FIG. 3, as closer to the edge of the well, a value of the threshold voltage VT becomes larger.
Since the NMOS transistors N1 and N2 of FIG. 1 are located at a distance of d1 and d2 (d2>d1), respectively, from the edge of the well, the threshold voltage VT of the NMOS transistor N1 is larger than that of the NMOS transistor N2. In the same way, in case of the PMOS transistors P1 and P2, the threshold voltage VT of the PMOS transistors P1 adjacent to the edge of the N-well is larger than that of the PMOS transistor P2.
FIG. 4 is a circuit diagram illustrating the bit line sense amplifier of FIG. 1.
The bit line sense amplifier comprises two CMOS inverters INV1 and INV2 which are cross-coupled. The inverter INV1 is comprised of the NMOS transistor N1 and the PMOS transistor P2, and the inverter INV2 is comprised of the NMOS transistor N2 and the PMOS transistor N1. An output terminal of the inverter INV1 is connected to an input terminal of the inverter INV2, and an output terminal of the inverter INV2 is connected to an input terminal of the inverter INV1. Here, the paired bit lines BL1 and /BL1 are connected to the output terminals of the inverters INV1 and INV2, respectively.
Here, if the NMOS transistor N1 has the same electrical characteristics as those of the NMOS transistor N2 and the PMOS transistor P1 has the same electrical characteristics as those of the PMOS transistor P2, the inverter INV1 has the same characteristics as those of the inverter INV2. As a result, although a small voltage is applied to the paired bit lines BL1 and /BL1, the small voltage can be amplified to a large voltage by a positive feedback of the inverters INV1 and INV2.
However, since the threshold voltages VT of the devices as different from each other as described above, a logic threshold voltage of the inverter INV1 becomes higher and a logic threshold voltage of the inverter INV2 becomes lower, so that the electrical characteristics of the inverter INV1 shift in an opposite direction to those of the inverter INV2.
As a result, the value of the offset voltage in the bit line sense amplifier becomes larger since the threshold voltage VT of the NMOS transistor N1 is added to that of the PMOS transistor P1.
That is, although the same voltage is applied to the paired bit lines BL1 and /BL1, the threshold voltage VT of the NMOS transistor N1 connected to the bit line BL1 is relatively large, so that current leaked into the NMOS transistor N1 is reduced. At the same time, since the threshold voltage VT of the PMOS transistor P2 is relatively small, current flowed from the PMOS transistor P2 is increased, so that the voltage of the bit line BL1 becomes higher gradually. As a result, the voltage of the bit line BL1 is constantly sensed as a high level signal.
As described above, since the offset voltage of the bit line sense amplifier adds to change of characteristics of the symmetrical devices in the arrangement of the devices in the conventional bit line sense amplifier, the offset voltage becomes larger, thereby reducing sensitivity of the bit line sense amplifier.